Initial

as68hc11/code/BOOTLOAD.ASM

@@ -0,0 +1,55 @@
+PORTD  equ 08h
+DDRD   equ 09h
+SPCR   equ 28h
+BAUD   equ 2Bh
+SCCR1  equ 2Ch
+SCCR2  equ 2Dh
+SCSR   equ 2Eh
+SCDAT  equ 2Fh
+PPROG  equ 3Bh
+TEST1  equ 3Eh
+CONFIG equ 3Fh
+EEPSTR equ 0F800h             ; start of EEPROM
+EEPEND equ 0FFFFh             ; end of EEPROM
+  org 0BF40h
+BEGIN equ *
+  lds  00FFh                  ; initialize the stack
+  ldx  1000h                  ; initialize x register for indexed access
+  bset ix,SPCR,20h            ; put port D in wire or mode
+  ldaa 0A2h                   ; initialize SCI & restart baud divider chain
+  staa ix,BAUD
+  ldaa 0Ch                    ; receiver & transmitter enabled
+  staa ix,SCCR2        
+  bset ix,SCCR2,01h           ; send break to signal start of download
+clrbrk:
+  brset ix,PORTD,01h,clrbrk   ; clear break as soon as start bit detected
+  bclr ix,SCCR2,01h           ; clear break
+waitchar1:
+  brclr ix,SCSR,20h,waitchar1 ; wait for RDRF
+  ldaa ix,SCDAT               ; read data
+  bne  NOTZERO                ; if data==00h (break or 00) jump to EEPROM
+  jmp EEPSTR                  ; jump to EEPROM
+NOTZERO equ *                 
+  cmpa 055h                   ; if data==55h skip download (ie) test mode
+  beq STAR
+  cmpa 0FFh                   ; if data=0FFh then /16 is correct baud rate
+  beq BAUDOK
+  bset ix,BAUD,033h           ; otherwise change to /104 (/13 &/8) 1200 @ 2MHZ
+BAUDOK equ *                  ; start the download
+  ldy 0000h                   ; initialize pointer
+BK2 equ *                     ; read in program and place in RAM
+waitchar2:
+  brclr ix,SCSR,20h,waitchar2 ; wait for RDRF
+  ldaa ix,SCDAT               ; 
+  staa iy,00h
+  staa ix,SCDAT               ; handshake
+  iny
+  cpy 0100h
+  bne BK2
+STAR equ *                    ; start user program
+  jmp [0000h]
+
+
+
+
+

as68hc11/code/BOOTLOAD.s19

@@ -0,0 +1,17 @@
+S12300008E00FFCE10001C282086A2A72B860CA72D1C2D011E0801FC1D2D011F2E20FCA6E6
+S12300202F26037EF8008155271E81FF27031C2B3318CE00001F2E20FCA62F18A700A72FF6
+S12300401808188C010026ED7E000001010101010101010101010101010101010101010131
+S123006001010101010101010101010101010101010101010101010101010101010101015C
+S123008001010101010101010101010101010101010101010101010101010101010101013C
+S12300A001010101010101010101010101010101010101010101010101010101010101011C
+S12300C00101010101010101010101010101010101010101010101010101010101010101FC
+S12300E00101010101010101010101010101010101010101010101010101010101010101DC
+S12301000101010101010101010101010101010101010101010101010101010101010101BC
+S123012001010101010101010101010101010101010101010101010101010101010101019C
+S123014001010101010101010101010101010101010101010101010101010101010101017C
+S123016001010101010101010101010101010101010101010101010101010101010101015C
+S123018001010101010101010101010101010101010101010101010101010101010101013C
+S12301A001010101010101010101010101010101010101010101010101010101010101011C
+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC

as68hc11/code/CODE1.ASM

@@ -0,0 +1,28 @@
+  org 1000h
+  bcc somewhere
+there:
+  bra where
+where:
+  bhi there
+  bcc lbcc
+hang:
+  beq hang
+this:
+  beq this
+lbcc:
+  jmp [1000h]
+  bsr hang
+  jmp somewhere
+  nop
+;  bcc somewhere
+  nop
+  org 1020h
+  rts
+  rts
+  rts
+  rts
+somewhere:
+
+
+
+

as68hc11/code/CODE1.s19

@@ -0,0 +1,17 @@
+S12300002422200022FC240427FE27FE7E10008DF77E102401013939393901010101010136
+S123002001010101010101010101010101010101010101010101010101010101010101019C
+S123004001010101010101010101010101010101010101010101010101010101010101017C
+S123006001010101010101010101010101010101010101010101010101010101010101015C
+S123008001010101010101010101010101010101010101010101010101010101010101013C
+S12300A001010101010101010101010101010101010101010101010101010101010101011C
+S12300C00101010101010101010101010101010101010101010101010101010101010101FC
+S12300E00101010101010101010101010101010101010101010101010101010101010101DC
+S12301000101010101010101010101010101010101010101010101010101010101010101BC
+S123012001010101010101010101010101010101010101010101010101010101010101019C
+S123014001010101010101010101010101010101010101010101010101010101010101017C
+S123016001010101010101010101010101010101010101010101010101010101010101015C
+S123018001010101010101010101010101010101010101010101010101010101010101013C
+S12301A001010101010101010101010101010101010101010101010101010101010101011C
+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC

as68hc11/code/CODE3.ASM

@@ -0,0 +1,14 @@
+EEPSTR equ 0F800h
+  org 1000h
+  jmp NOTZERO
+;  jmp EEPSTR
+;  nop
+;  nop
+;  nop
+;  nop
+NOTZERO equ *
+  rts
+
+
+
+

as68hc11/code/CODE3.BIN

@@ -0,0 +1 @@
+~9

as68hc11/code/CODE4.ASM

@@ -0,0 +1,7 @@
+;  bcc ERASE
+;  jsr there
+  bcc there
+there:
+
+
+

as68hc11/code/Code.asm

@@ -0,0 +1,2 @@
+cmpa 00h
+

as68hc11/code/PROTO.ASM

@@ -0,0 +1,35 @@
+PORTD  equ 08h
+DDRD   equ 09h
+SPCR   equ 28h
+BAUD   equ 2Bh
+SCCR1  equ 2Ch
+SCCR2  equ 2Dh
+SCSR   equ 2Eh
+SCDAT  equ 2Fh
+PPROG  equ 3Bh
+TEST1  equ 3Eh
+CONFIG equ 3Fh
+EEPSTR equ 0F800h             ; start of EEPROM
+EEPEND equ 0FFFFh             ; end of EEPROM
+  org 0000h
+BEGIN equ *
+  lds  00FFh                  ; initialize the stack
+  ldx  1000h                  ; initialize x register for indexed access
+  bset ix,SPCR,20h            ; put port D in wire or mode
+  ldaa 0A2h                   ; initialize SCI & restart baud divider chain
+  staa ix,BAUD
+  ldaa 0Ch                    ; receiver & transmitter enabled
+  staa ix,SCCR2        
+  bset ix,SCCR2,01h           ; send break to signal start of download
+clrbrk:
+  brset ix,PORTD,01h,clrbrk   ; clear break as soon as start bit detected
+  bclr ix,SCCR2,01h           ; clear break
+waitchar1:
+  brclr ix,SCSR,20h,waitchar1 ; wait for RDRF
+  ldaa ix,SCDAT               ; read data
+  jmp BEGIN                   ; do it forever
+
+
+
+
+

as68hc11/code/PROTO.s19

@@ -0,0 +1,17 @@
+S12300008E00FFCE10001C282086A2A72B860CA72D1C2D011E0801FC1D2D011F2E20FCA6E6
+S12300202F7E000001010101010101010101010101010101010101010101010101010101F3
+S123004001010101010101010101010101010101010101010101010101010101010101017C
+S123006001010101010101010101010101010101010101010101010101010101010101015C
+S123008001010101010101010101010101010101010101010101010101010101010101013C
+S12300A001010101010101010101010101010101010101010101010101010101010101011C
+S12300C00101010101010101010101010101010101010101010101010101010101010101FC
+S12300E00101010101010101010101010101010101010101010101010101010101010101DC
+S12301000101010101010101010101010101010101010101010101010101010101010101BC
+S123012001010101010101010101010101010101010101010101010101010101010101019C
+S123014001010101010101010101010101010101010101010101010101010101010101017C
+S123016001010101010101010101010101010101010101010101010101010101010101015C
+S123018001010101010101010101010101010101010101010101010101010101010101013C
+S12301A001010101010101010101010101010101010101010101010101010101010101011C
+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC

as68hc11/code/SWI.ASM

@@ -0,0 +1,93 @@
+; AUTHOR: SEAN KESSLER                        DATE:04/17/1999
+; PROGRAM: TALK.ASM
+; PLATFORM:M68HC11
+; FUNCTION:TEST SWI INSTRUCTION
+
+EVENTCHAR    equ 000h
+EVENTWORD    equ 001h
+EVENTDWORD   equ 002h
+EVENTVARCHAR equ 003h
+EVENTREGS    equ 004h
+EVENTEND     equ 0FFh
+
+SCDR         equ 0102Fh     ; data register
+SCSR         equ 0102Eh     ; status register
+EEPROM       equ 0F800h     ; start of EEPROM 
+RAM          equ 00000h     ; base of code
+SWI          equ 0FFF6h     ; software interrupt vector lives here
+REGS         equ 01000h     ; start of REGS
+CONFIG       equ 0103Fh     ; CONFIG marks the end of REGS
+BPROT        equ 01035h     ; BPROT
+PPROG        equ 0103Bh     ; PPROG
+MEMLOC       equ 80h        ; 80h,81h are scratch pad
+STACK        equ RAM+0FFh   ; stack expands down from here
+  org RAM                   ; base of code
+BEGIN equ *
+  lds STACK                 ; initialize the stack
+START equ *                 ; start sync address
+  bsr WRITEREGSEVENT        ; 
+  bsr WRITEENDEVENT         ; 
+  jmp START                 ; do it forever
+WRITESTRING equ *
+  rts
+WRITEENDEVENT equ *         ; write end event to the SCI
+  ldab EVENTEND             ; load the event type into register B
+  bsr WRITECHAR             ; write the event to the SCI
+  rts                       ; return to caller
+WRITECHAREVENT equ *        ; write a character event to the SCI
+  pshb                      ; save contents of register B 
+  ldab EVENTCHAR            ; load event type into register B
+  bsr WRITECHAR             ; write the event type to the SCI
+  pulb                      ; restore contents of register B
+  bsr WRITECHAR             ; write the event data to the SCI
+  rts                       ; return to caller
+WRITEREGSEVENT equ *        ; write the registers out to the SCI
+  ldab EVENTREGS            ; load value of EVENTREGS into register B
+  bsr WRITECHAR             ; send the value out to the SCI
+  ldd REGS                  ; get address of REGS into register D   
+CONTINUEREGS equ *          ; sync address
+  psha                      ; save register A 
+  pshb                      ; save register B
+  xgdx                      ; exchange D with X (X has current address)
+  ldab ix,00h               ; load byte at address in X to B register
+  bsr WRITECHAR             ; send the byte out to the SCI     
+  pulb                      ; restore register B
+  pula                      ; restore register A
+  addd 01h                  ; increment value in register D
+  cpd CONFIG                ; compare this value to address of CONFIG register
+  ble CONTINUEREGS          ; if it's less than or equal then keep going
+  bsr WAITCHAR              ; wait for a character
+  rts                       ; return to caller
+WRITECHAR equ *             ; write character from B register to SCDR
+  ldaa [SCSR]               ; get status into A register
+  anda 80h                  ; check TDRE (transmit data register empty)
+  beq WRITECHAR             ; keep trying until SCI is ready for character
+  stab [SCDR]               ; write character from B register to SCDR
+  rts                       ; return to caller
+WRITEWORD equ *             ; write word in register D to the SCI
+  psha                      ; save contents of register A
+  bsr WRITECHAR             ; write contents of B (hi byte)
+  pulb                      ; restore contents of register A into B
+  bsr WRITECHAR             ; write contents of B (lo byte)
+  rts                       ; return to caller
+READCHAR equ *              ; read character from SCDR into B register
+  psha                      ; save contents of register A
+RDCLOOP equ *               ; wait loop
+  ldaa [SCSR]               ; get status into A register
+  anda 20h                  ; is RDRF set (indicates we have char)
+  beq RDCLOOP               ; keep trying until RDRF is set
+  ldab [SCDR]               ; load character into B register  
+  pula                      ; save contents of register A
+  rts                       ; return to caller
+WAITCHAR equ *              ; wait for a character
+  psha                      ; save contents of register A
+  pshb                      ; save contents of register B
+  bsr READCHAR              ; read a character into B register
+  pulb                      ; restore contents of register B
+  pula                      ; restore contents of register A
+  rts                       ; return to caller
+
+
+
+
+

as68hc11/code/SWI.s19

@@ -0,0 +1,17 @@
+S12300008E00FF8D148D047E000339C6FF8D263937C6008D20338D1D39C6048D18CC1000A7
+S123002036378FE6008D0E3332C300011A83103F2FEE8D2039B6102E848027F9F7102F39A0
+S1230040368DF2338DEF3936B6102E842027F9F6102F323936378DEF3332390101010101E5
+S123006001010101010101010101010101010101010101010101010101010101010101015C
+S123008001010101010101010101010101010101010101010101010101010101010101013C
+S12300A001010101010101010101010101010101010101010101010101010101010101011C
+S12300C00101010101010101010101010101010101010101010101010101010101010101FC
+S12300E00101010101010101010101010101010101010101010101010101010101010101DC
+S12301000101010101010101010101010101010101010101010101010101010101010101BC
+S123012001010101010101010101010101010101010101010101010101010101010101019C
+S123014001010101010101010101010101010101010101010101010101010101010101017C
+S123016001010101010101010101010101010101010101010101010101010101010101015C
+S123018001010101010101010101010101010101010101010101010101010101010101013C
+S12301A001010101010101010101010101010101010101010101010101010101010101011C
+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC

as68hc11/code/TALK.ASM

@@ -0,0 +1,145 @@
+; AUTHOR: SEAN KESSLER                   DATE:04/17/1999
+; PROGRAM: TALK.ASM
+; PLATFORM:M68HC11
+; FUNCTION:TEST SWI INSTRUCTION
+
+EVENTCHAR    equ 000h
+EVENTWORD    equ 001h
+EVENTDWORD   equ 002h
+EVENTVARCHAR equ 003h
+EVENTREGS    equ 004h
+EVENTSTRING  equ 005h
+EVENTEND     equ 0FFh
+
+SCDR         equ 0102Fh      ; data register
+SCSR         equ 0102Eh      ; status register
+EEPROM       equ 0F800h      ; start of EEPROM 
+RAM          equ 00000h      ; base of code
+RAMSIZE      equ 000FFh      ; extent of RAM
+DATASIZE     equ 00040h      ; extent of DATA 40h=64d
+SWI          equ 0FFF6h      ; software interrupt vector lives here
+REGS         equ 01000h      ; start of REGS
+CONFIG       equ 0103Fh      ; CONFIG marks the end of REGS
+BPROT        equ 01035h      ; BPROT
+PPROG        equ 0103Bh      ; PPROG
+MEMLOC       equ 80h         ; 80h,81h are scratch pad
+
+
+STACK        equ RAM+RAMSIZE ; stack expands down from end of RAM
+DATA         equ 000C1h      ; data expands upward from 193d
+
+RSTVHI       equ 0FFFFh      ; hi byte of reset vector
+RSTVLO       equ 0FFFEh      ; lo byte of reset vector
+  org RAM                    ; base of code
+BEGIN equ *
+  lds STACK                 ; initialize the stack
+START equ *                 ; start sync address
+  ldx szTitle
+  bsr WRITESTRINGEVENT
+
+;  ldab '*'
+;  bsr WRITECHAREVENT
+
+
+;  ldab [EEPROM]            ; load contents of RAM byte into register b
+;  bsr WRITECHAREVENT        ; write out character
+;  ldab 0005h
+;  stab [EEPROM]            ; set zero into ram
+;  ldab [EEPROM]            ; load contents of RAM byte into register b
+;  bsr WRITECHAREVENT        ; write out character
+  
+
+;  ldab 'S'
+;  bsr WRITECHAREVENT
+;  bsr WRITEENDEVENT
+
+
+  bsr WRITEREGSEVENT        ; 
+  bsr WRITEENDEVENT         ; 
+  jmp START                 ; do it forever
+
+szTitle  rmb 'A',00h
+
+;******************** SCI SUPPORT SUBROUTINES ******************
+WRITEENDEVENT equ *         ; write end event to the SCI
+  ldab EVENTEND             ; load the event type into register B
+  bsr WRITECHAR             ; write the event to the SCI
+  rts                       ; return to caller
+WRITESTRINGEVENT equ *      ; write null terminated string to the SCI
+  pshy                      ; save register y
+  pshb                      ; save register b
+  ldab EVENTSTRING          ; load event type into register b
+  bsr WRITECHAR             ; write the event type to the SCI
+WRITESTRINGEVENTLP equ *    ; sync loop
+  ldab ix,00                ; load [ix+0] to register y
+  bsr WRITECHAR             ; write the character to the SCI
+  cmpb 00h                  ; check it the character is zero
+  beq WRITESTRINGEVENTEND   ; if it's zero we're all done
+  inx                       ; increment along ix
+  jmp WRITESTRINGEVENTLP    ; continue along until a null is encountered
+WRITESTRINGEVENTEND equ *   ; sync address
+  pulb                      ; restore register b
+  puly                      ; restore register y
+  rts                       ; return to caller
+WRITECHAREVENT equ *        ; write character event to the SCI
+  pshb                      ; save contents of register B 
+  ldab EVENTCHAR            ; load event type into register B
+  bsr WRITECHAR             ; write the event type to the SCI
+  pulb                      ; restore contents of register B
+  bsr WRITECHAR             ; write the event data to the SCI
+  rts                       ; return to caller
+WRITEREGSEVENT equ *        ; write the registers out to the SCI
+  ldab EVENTREGS            ; load value of EVENTREGS into register B
+  bsr WRITECHAR             ; send the value out to the SCI
+  ldd REGS                  ; get address of REGS into register D   
+CONTINUEREGS equ *          ; sync address
+  psha                      ; save register A 
+  pshb                      ; save register B
+  xgdx                      ; exchange D with X (X has current address)
+  ldab ix,00h               ; load byte at address in X to B register
+  bsr WRITECHAR             ; send the byte out to the SCI     
+  pulb                      ; restore register B
+  pula                      ; restore register A
+  addd 01h                  ; increment value in register D
+  cpd CONFIG                ; compare this value to address of CONFIG register
+  ble CONTINUEREGS          ; if it's less than or equal then keep going
+  bsr WAITCHAR              ; wait for a character
+  rts                       ; return to caller
+WRITECHAR equ *             ; write character from B register to SCDR
+  ldaa [SCSR]               ; get status into A register
+  anda 80h                  ; check TDRE (transmit data register empty)
+  beq WRITECHAR             ; keep trying until SCI is ready for character
+  stab [SCDR]               ; write character from B register to SCDR
+  rts                       ; return to caller
+WRITEWORD equ *             ; write word in register D to the SCI
+  psha                      ; save contents of register A
+  bsr WRITECHAR             ; write contents of B (hi byte)
+  pulb                      ; restore contents of register A into B
+  bsr WRITECHAR             ; write contents of B (lo byte)
+  rts                       ; return to caller
+READCHAR equ *              ; read character from SCDR into B register
+  psha                      ; save contents of register A
+RDCLOOP equ *               ; wait loop
+  ldaa [SCSR]               ; get status into A register
+  anda 20h                  ; is RDRF set (indicates we have char)
+  beq RDCLOOP               ; keep trying until RDRF is set
+  ldab [SCDR]               ; load character into B register  
+  pula                      ; restore contents of register A
+  rts                       ; return to caller
+WAITCHAR equ *              ; wait for a character
+  psha                      ; save contents of register A
+  pshb                      ; save contents of register B
+  bsr READCHAR              ; read a character into B register
+  pulb                      ; restore contents of register B
+  pula                      ; restore contents of register A
+  rts                       ; return to caller
+
+
+
+
+
+
+
+
+
+

as68hc11/code/TALK.s19

@@ -0,0 +1,17 @@
+S12300008E00FFCE000F8D0E8D2C8D057E00034100C6FF8D3D39183C37C6058D35E6008D77
+S123002031C1002704087E001D3318383937C6008D20338D1D39C6048D18CC100036378F39
+S1230040E6008D0E3332C300011A83103F2FEE8D2039B6102E848027F9F7102F39368DF2C7
+S1230060338DEF3936B6102E842027F9F6102F323936378DEF333239010101010101010177
+S123008001010101010101010101010101010101010101010101010101010101010101013C
+S12300A001010101010101010101010101010101010101010101010101010101010101011C
+S12300C00101010101010101010101010101010101010101010101010101010101010101FC
+S12300E00101010101010101010101010101010101010101010101010101010101010101DC
+S12301000101010101010101010101010101010101010101010101010101010101010101BC
+S123012001010101010101010101010101010101010101010101010101010101010101019C
+S123014001010101010101010101010101010101010101010101010101010101010101017C
+S123016001010101010101010101010101010101010101010101010101010101010101015C
+S123018001010101010101010101010101010101010101010101010101010101010101013C
+S12301A001010101010101010101010101010101010101010101010101010101010101011C
+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC

as68hc11/code/TALK3.ASM

@@ -0,0 +1,69 @@
+; AUTHOR: SEAN KESSLER                        DATE:04/17/1999
+; PROGRAM: TALK.ASM
+; PLATFORM:M68HC11
+; FUNCTION:TEST SCI BASED COMMUNICATIONS ON CONTROLLER
+BAUD   equ 0102Bh    ; baud register
+SCCR2  equ 0102Dh    ; main control register for SCI subsystem
+SCSR   equ 0102Eh    ; status register
+SCDR   equ 0102Fh    ; data register
+SPCR   equ 01028h
+PORTD  equ 01008h    ; io configuration
+RAM    equ 00000h    ; base of code
+EEPROM equ 0F800h    ; base of EEPROM
+STACK  equ RAM+0FFh  ; stack expands down from here
+LENGTH equ 0Bh
+  org RAM                   ; base of code
+  lds STACK                 ; initialize the stack
+START equ *
+;  bsr INITSCI               ; initialize communications on controller
+;  bsr GETACK                ; send break to host and wait for acknowledgement
+  ldab 'S'                  ; load 'S' into register B
+  bsr WRITECHAR             ; send the character
+  ldab 'E'                  ; load 'E' into register B
+  bsr WRITECHAR             ; send the character
+  ldab 'A'                  ; load 'A' into register B
+  bsr WRITECHAR             ; send the character
+  ldab 'N'                  ; load 'N' into register B
+  bsr WRITECHAR             ; send the character
+  jmp START                 ; do it forever
+READCHAR equ *              ; read character from SCDR into B register
+  ldab 00h                  ; clear out B register
+  ldaa [SCSR]               ; get status into A register
+  anda 20h                  ; is RDRF set (indicates we have char)
+  beq READCHAR              ; keep trying until RDRF is set
+  ldab [SCDR]               ; load character into B register  
+  rts                       ; return to caller
+WRITECHAR equ *             ; write character to SCDR from B register
+  ldaa [SCSR]               ; get status into A register
+  anda 80h                  ; check TDRE (transmit data register empty)
+  beq WRITECHAR             ; keep trying until SCI is ready for character
+  stab [SCDR]               ; write character from B register to SCDR
+  rts                       ; return to caller
+INITSCI equ *               ; controller initialization
+  ldx SPCR                  ; load SPSC address into x register
+  bset ix,0h,20h            ; put port D in wire or mode
+  ldaa 0A2h                 ; initialize SCI & restart BAUD rate divider
+  staa [BAUD]               ; do it
+  ldaa 0Ch                  ; enable transmit/receive
+  staa [SCCR2]              ; do it
+  rts                       ; return to caller
+GETACK equ *                ; wait for signal from user
+  ldx SCCR2                 ; load SCCR2 address into index register x
+  bset ix,00h,01h           ; set bit zero in SCCR2, send break
+  ldx PORTD                 ; load PORTD address into index register x
+clrbrk equ *                ; sync address
+  brset ix,00h,01h,clrbrk   ; wait for start bit
+  ldx SCCR2                 ; load SCCR2 address into x register
+  bclr ix,00h,01h           ; clear the break
+waitchar equ *              ; sync address
+  ldx SCSR                  ; load address of SCDR into x register
+  brclr ix,00h,20h,waitchar ; wait for a character
+  ldaa [SCDR]               ; load character into register A
+  rts                       ; return to caller
+
+
+
+
+
+
+

as68hc11/code/TEST.BIN

@@ -0,0 +1 @@
+

as68hc11/code/TEST2.ASM

@@ -0,0 +1,34 @@
+  org 1000h             ; set base of code to 1000h
+  bcc start             ; jump target
+  jmp start
+  jmp start
+  rts                   ; return from subroutine
+  rts                   ; return from subroutine
+;  start equ *           ; macro reference
+;  start equ 70h
+start:
+  nop                   ; no operation
+  nop                   ; no operation
+  nop                   ; no operation
+  nop                   ; no operation
+  bcc start
+  jmp start
+  rts                   ; return from subroutine   
+  jmp foo
+  org 2000h
+  nop
+  nop
+  nop
+  nop
+  jmp start
+foo:
+
+
+
+
+
+
+
+
+
+

as68hc11/code/TEST2.BIN

@@ -0,0 +1,4 @@
+$~
+~
+99



$<24>~
+9~ 



~

as68hc11/code/TEST2.s19

@@ -0,0 +1,3 @@
+S11A100024087E100A7E100A39390101010124FA7E100A397E20077F
+S10A2000010101017E100A59
+S9030000FC

as68hc11/code/Test.asm

@@ -0,0 +1,7 @@
+  org 0012h
+  inx
+  org 0016h
+  inx
+
+  
+

as68hc11/code/code2.asm

@@ -0,0 +1,36 @@
+PORTD  equ 08h
+DDRD   equ 09h
+TOC1   equ 16h
+SPCR   equ 28h
+BAUD   equ 2Bh
+SCCR1  equ 2Ch
+SCCR2  equ 2Dh
+SCSR   equ 2Eh
+SCDAT  equ 2Fh
+PPROG  equ 3Bh
+CONFIG equ 3Fh
+
+EEPSTR  equ 0B600h   ; start of EEPROM
+EEPEND  equ 0B7FFh   ; end of EEPROM
+RAMSTR  equ 00000h
+RAMEND  equ 001FFh
+DELAYS  equ 3504     ; delay at slow baud
+DELAYF  equ 539      ; delay at fast baud
+
+there:
+   bcc ERASE
+;  bcc there          ; ok  
+;  staa ix,ERASE      ; needs another pass to resolve forward reference 
+;  HERE equ *         ; ok
+;  staa ix,SCDAT      ; ok
+;  rts                ; return to caller 
+ERASE  equ *         ; ERASE procedure
+  bset ix,PPROG+08h,20h  ; this generates incorrect code
+;  bset ix,SPCR,20h            ; put port D in wire or mode
+  rts                ; return to caller  
+
+
+
+
+
+

as68hc11/code/eeprom.asm

@@ -0,0 +1,73 @@
+; AUTHOR: SEAN KESSLER                        DATE:01/10/2001
+; PROGRAM: EEPROM.ASM
+; PLATFORM:M68HC11E2FN
+; LANGUAGE:CUSTOM ASSEMBLER
+; FUNCTION:TEST EEPROM READ/WRITE
+
+RAM          equ 00000h      ; base of code
+RAMSIZE      equ 000FFh      ; extent of RAM
+STACK        equ RAM+RAMSIZE ; stack expands down from end of RAM
+PORTB        equ 01004h      ; address of PORTB register
+EEPROM       equ 0F800h      ; start of EEPROM 
+PPROG        equ 0103Bh      ; PPROG register
+EEPGM        equ 00003h      ; EEPROM Programming Voltage Enable
+EELAT        equ 00002h      ; EEPROM Latch Control
+  org RAM                    ; base of code
+BEGIN equ *
+  lds STACK                  ; initialize the stack
+START equ *                  ; start sync address
+loop equ *
+
+  ldab 01h                   ; move 1 into register b
+  stab [PORTB]               ; light b0
+  bsr DELAY100
+;  bsr DELAY1K                ; pause
+
+  ldab 02h                   ; move 2 into register b  
+  stab [PORTB]               ; light b1
+  bsr DELAY100
+;  bsr DELAY1K                ; pause
+
+  jmp loop
+
+END equ *                   ; need to figure out how to enable stop
+  jmp END                   ; do it forever
+; ********************* write data to EEPROM location ******************************
+EEPROMW equ *               ; register a contains data, x contains eeprom address
+  ldab EELAT                ; move EELAT enable into register b
+  stab [PPROG]              ; move EELAT enable into PPROG register
+  staa ix,0                 ; store contents of register a into EEPROM address at ix
+  ldab EEPGM                ; move EEPGM enable bit into register b
+  stab [PPROG]              ; move EEPGM enable bits into PPROG register
+  bsr DELAY10               ; allow charge pump to charge
+  clr [PPROG]               ; turn off high voltage & set to read mode
+  rts
+; ********************** DELAY ROUTINES ************************
+DELAY10 equ *               ; 10ms delay @ 2.1 mhz
+  pshy                      ; save register y
+  ldy 0BB8h                 ; load loop counter into y register
+DELAY10LOOP equ *           ; loop counter sync address
+  dey                       ; decrement counter 
+  bne DELAY10LOOP           ; loop until zero in y
+  puly                      ; restore register y
+  rts                       ; return to caller
+DELAY1K equ *               ; 1000ms delay @ 2.1 mhz
+  pshy                      ; save register y
+  ldy 0Ah                   ; load 10d into register y
+DELAY1KLP equ *             ; loop counter sync address
+  bsr DELAY100              ; call 100 ms delay
+  dey                       ; decrement register y
+  bne DELAY1KLP             ; continue
+  puly                      ; restore register y
+  rts                       ; return to caller
+DELAY100 equ *              ; 100 ms @ 2.1 mhz
+  pshx                      ; save register x
+  ldx 07530h                ; load loop counter into register x
+DELAY100LP equ *            ; loop counter sync address
+  dex                       ; decrement register x
+  bne DELAY100LP            ; continue
+  pulx                      ; restore register x
+  rts                       ; return to caller
+
+
+

as68hc11/code/eeprom.s19

@@ -0,0 +1,17 @@
+S12300008E00FFC601F710048D3BC602F710048D347E00037E0014C602F7103BA700C60394
+S1230020F7103B8D047F103B39183C18CE0BB8180926FC183839183C18CE000A8D07180924
+S123004026FA1838393CCE75300926FD383901010101010101010101010101010101010195
+S123006001010101010101010101010101010101010101010101010101010101010101015C
+S123008001010101010101010101010101010101010101010101010101010101010101013C
+S12300A001010101010101010101010101010101010101010101010101010101010101011C
+S12300C00101010101010101010101010101010101010101010101010101010101010101FC
+S12300E00101010101010101010101010101010101010101010101010101010101010101DC
+S12301000101010101010101010101010101010101010101010101010101010101010101BC
+S123012001010101010101010101010101010101010101010101010101010101010101019C
+S123014001010101010101010101010101010101010101010101010101010101010101017C
+S123016001010101010101010101010101010101010101010101010101010101010101015C
+S123018001010101010101010101010101010101010101010101010101010101010101013C
+S12301A001010101010101010101010101010101010101010101010101010101010101011C
+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC

as68hc11/code/equates.inc

@@ -0,0 +1,5 @@
+RAM    equ 0000h
+THIS   equ 0010h
+END    equ 0020h
+SCSR   equ 2Eh
+PORTB  equ 1004h      ; address of PORTB register

as68hc11/code/equates.s19

@@ -0,0 +1,17 @@
+S12300000101010101010101010101010101010101010101010101010101010101010101BC
+S123002001010101010101010101010101010101010101010101010101010101010101019C
+S123004001010101010101010101010101010101010101010101010101010101010101017C
+S123006001010101010101010101010101010101010101010101010101010101010101015C
+S123008001010101010101010101010101010101010101010101010101010101010101013C
+S12300A001010101010101010101010101010101010101010101010101010101010101011C
+S12300C00101010101010101010101010101010101010101010101010101010101010101FC
+S12300E00101010101010101010101010101010101010101010101010101010101010101DC
+S12301000101010101010101010101010101010101010101010101010101010101010101BC
+S123012001010101010101010101010101010101010101010101010101010101010101019C
+S123014001010101010101010101010101010101010101010101010101010101010101017C
+S123016001010101010101010101010101010101010101010101010101010101010101015C
+S123018001010101010101010101010101010101010101010101010101010101010101013C
+S12301A001010101010101010101010101010101010101010101010101010101010101011C
+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC

as68hc11/code/led.asm

@@ -0,0 +1,60 @@
+RAM    equ 0000h
+THIS   equ 0010h
+END    equ 0020h
+SCSR   equ 2Eh
+PORTB  equ 1004h      ; address of PORTB register
+  org RAM        
+  jmp BEGIN
+BEGIN:
+  ldab 01h            ; move 1 into register b
+  stab [PORTB]        ; light b0
+
+  ldab 03h            ; move 1 into register b
+  stab [PORTB]        ; light b0
+
+  bsr DELAY1K
+  ldab 00h            ; move 0 into register b
+  stab [PORTB]        ; turn off bo
+  bsr DELAY1K
+  jmp BEGIN
+
+;  ldaa [PORTB]        ; move contents of PORTB into register a
+;  ldab [PORTB]    ; 
+
+  rts
+DELAY10 equ *               ; 10ms delay @ 2.1 mhz
+  pshy                      ; save register y
+  ldy 0BB8h                 ; load loop counter into y register
+DELAY10LOOP equ *           ; loop counter sync address
+  dey                       ; decrement counter 
+  bne DELAY10LOOP           ; loop until zero in y
+  puly                      ; restore register y
+  rts                       ; return to caller
+DELAY1K equ *               ; 1000ms delay @ 2.1 mhz
+  pshy                      ; save register y
+  ldy 0Ah                   ; load 10d into register y
+DELAY1KLP equ *             ; loop counter sync address
+  bsr DELAY100              ; call 100 ms delay
+  dey                       ; decrement register y
+  bne DELAY1KLP             ; continue
+  puly                      ; restore register y
+  rts                       ; return to caller
+DELAY100 equ *              ; 100 ms @ 2.1 mhz
+  pshx                      ; save register x
+  ldx 07530h                ; load loop counter into register x
+DELAY100LP equ *            ; loop counter sync address
+  dex                       ; decrement register x
+  bne DELAY100LP            ; continue
+  pulx                      ; restore register x
+  rts                       ; return to caller
+
+
+
+
+
+
+
+
+
+
+

as68hc11/code/led.s19

@@ -0,0 +1,17 @@
+S12300007E0003C601F71004C603F710048D18C600F710048D117E000339183C18CE0BB8EA
+S1230020180926FC183839183C18CE000A8D07180926FA1838393CCE75300926FD38390101
+S123004001010101010101010101010101010101010101010101010101010101010101017C
+S123006001010101010101010101010101010101010101010101010101010101010101015C
+S123008001010101010101010101010101010101010101010101010101010101010101013C
+S12300A001010101010101010101010101010101010101010101010101010101010101011C
+S12300C00101010101010101010101010101010101010101010101010101010101010101FC
+S12300E00101010101010101010101010101010101010101010101010101010101010101DC
+S12301000101010101010101010101010101010101010101010101010101010101010101BC
+S123012001010101010101010101010101010101010101010101010101010101010101019C
+S123014001010101010101010101010101010101010101010101010101010101010101017C
+S123016001010101010101010101010101010101010101010101010101010101010101015C
+S123018001010101010101010101010101010101010101010101010101010101010101013C
+S12301A001010101010101010101010101010101010101010101010101010101010101011C
+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC

as68hc11/code/macros.inc

@@ -0,0 +1,26 @@
+DELAY10 equ *               ; 10ms delay @ 2.1 mhz
+  pshy                      ; save register y
+  ldy 0BB8h                 ; load loop counter into y register
+DELAY10LOOP equ *           ; loop counter sync address
+  dey                       ; decrement counter 
+  bne DELAY10LOOP           ; loop until zero in y
+  puly                      ; restore register y
+  rts                       ; return to caller
+DELAY1K equ *               ; 1000ms delay @ 2.1 mhz
+  pshy                      ; save register y
+  ldy 0Ah                   ; load 10d into register y
+DELAY1KLP equ *             ; loop counter sync address
+  bsr DELAY100              ; call 100 ms delay
+  dey                       ; decrement register y
+  bne DELAY1KLP             ; continue
+  puly                      ; restore register y
+  rts                       ; return to caller
+DELAY100 equ *              ; 100 ms @ 2.1 mhz
+  pshx                      ; save register x
+  ldx 07530h                ; load loop counter into register x
+DELAY100LP equ *            ; loop counter sync address
+  dex                       ; decrement register x
+  bne DELAY100LP            ; continue
+  pulx                      ; restore register x
+  rts                       ; return to caller
+

as68hc11/code/test.s19

@@ -0,0 +1,3 @@
+S104001208E1
+S104001608DD
+S9030000FC

as68hc11/code/test1.asm

@@ -0,0 +1,23 @@
+RAM    equ 0000h
+  org RAM
+  inx
+  bra prone
+prthree:
+  ldab 03h
+  bra prend
+prtwo:
+  ldab 02h
+  bra prthree
+prone:
+  ldab 01h
+  bra prtwo
+prend:
+  rts
+
+
+
+
+
+
+
+

as68hc11/code/test1.bin

@@ -0,0 +1 @@
+ <08> <08> <20><>
 <20>9

as68hc11/code/test1.s19

@@ -0,0 +1,17 @@
+S1230000082008C6032008C60220F8C60120F83901010101010101010101010101010101B3
+S123002001010101010101010101010101010101010101010101010101010101010101019C
+S123004001010101010101010101010101010101010101010101010101010101010101017C
+S123006001010101010101010101010101010101010101010101010101010101010101015C
+S123008001010101010101010101010101010101010101010101010101010101010101013C
+S12300A001010101010101010101010101010101010101010101010101010101010101011C
+S12300C00101010101010101010101010101010101010101010101010101010101010101FC
+S12300E00101010101010101010101010101010101010101010101010101010101010101DC
+S12301000101010101010101010101010101010101010101010101010101010101010101BC
+S123012001010101010101010101010101010101010101010101010101010101010101019C
+S123014001010101010101010101010101010101010101010101010101010101010101017C
+S123016001010101010101010101010101010101010101010101010101010101010101015C
+S123018001010101010101010101010101010101010101010101010101010101010101013C
+S12301A001010101010101010101010101010101010101010101010101010101010101011C
+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC

as68hc11/code/test3.asm

@@ -0,0 +1,53 @@
+RAM    equ 0000h
+EEPROM equ 0014h
+  org RAM
+RAMSTART equ *
+  bcc prdone     ; this generates incorrect offset for the branch
+  inx
+  inx
+  inx
+  inx
+rmdone:
+;  org EEPROM
+EESTART equ *
+  bcc prdone      ; this generates correct offset for the branch
+  inx
+  inx
+  inx
+  inx
+;prdone:
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+  inx
+prdone:
+  ldab 01h
+  cmpb 01h
+  beq prdone
+
+
+
+
+
+

as68hc11/code/test3.bin

@@ -0,0 +1 @@
+$#$<08>
<01>
'<27>

as68hc11/code/test3.s19

@@ -0,0 +1,3 @@
+S1230000242308080808241D08080808080808080808080808080808080808080808080874
+S10E00200808080808C601C10127FAFF
+S9030000FC

as68hc11/code/test4.asm

@@ -0,0 +1,19 @@
+RAM    equ 0000h
+THIS   equ 0010h
+THAT   equ 0020h
+OTHER  equ 0030h
+  org RAM
+  bra THIS
+  org THIS
+  bra THAT
+  org THAT
+  bra OTHER
+  org OTHER
+  bra prdone
+prdone:
+  clrb
+
+
+
+
+

as68hc11/code/test4.s19

@@ -0,0 +1,17 @@
+S1230000200E0000000000000000000000000000200E000000000000000000000000000080
+S1230020200E000000000000000000000000000020005F000000000000000000000000000F
+S123004000000000000000000000000000000000000000000000000000000000000000009C
+S123006000000000000000000000000000000000000000000000000000000000000000007C
+S123008000000000000000000000000000000000000000000000000000000000000000005C
+S12300A000000000000000000000000000000000000000000000000000000000000000003C
+S12300C000000000000000000000000000000000000000000000000000000000000000001C
+S12300E00000000000000000000000000000000000000000000000000000000000000000FC
+S12301000000000000000000000000000000000000000000000000000000000000000000DC
+S12301200000000000000000000000000000000000000000000000000000000000000000BC
+S123014000000000000000000000000000000000000000000000000000000000000000009C
+S123016000000000000000000000000000000000000000000000000000000000000000007C
+S123018000000000000000000000000000000000000000000000000000000000000000005C
+S12301A000000000000000000000000000000000000000000000000000000000000000003C
+S12301C000000000000000000000000000000000000000000000000000000000000000001C
+S12301E00000000000000000000000000000000000000000000000000000000000000000FC
+S9030000FC

as68hc11/code/test5.LST

@@ -0,0 +1,11 @@
+  ADDR B1 B2 B3 B4 thrass11.tmp                                     PAGE       1
+
+                   RAM    equ $0000
+                   THIS   equ $0010
+                     org RAM
+  0000 20 0E         bra THIS
+
+  Symbol Table 
+
+  THIS               0010
+  RAM                0000

as68hc11/code/test5.asm

@@ -0,0 +1,25 @@
+RAM    equ 0000h
+THIS   equ 0010h
+THAT   equ 0020h
+OTHER  equ 0030h
+LONG   equ 0080h
+  org RAM
+  bra THIS
+  org THIS
+  bra OTHER
+  org THAT
+princ:
+  inx
+  bra end
+  org OTHER
+  bra princ
+end:
+  bra LONG
+  org LONG
+  ldab LONG
+
+
+
+
+
+

as68hc11/code/test5.s19

@@ -0,0 +1,17 @@
+S1230000200E0000000000000000000000000000201E000000000000000000000000000070
+S123002008200F0000000000000000000000000020EE204E00000000000000000000000009
+S123004000000000000000000000000000000000000000000000000000000000000000009C
+S123006000000000000000000000000000000000000000000000000000000000000000007C
+S1230080C68000000000000000000000000000000000000000000000000000000000000016
+S12300A000000000000000000000000000000000000000000000000000000000000000003C
+S12300C000000000000000000000000000000000000000000000000000000000000000001C
+S12300E00000000000000000000000000000000000000000000000000000000000000000FC
+S12301000000000000000000000000000000000000000000000000000000000000000000DC
+S12301200000000000000000000000000000000000000000000000000000000000000000BC
+S123014000000000000000000000000000000000000000000000000000000000000000009C
+S123016000000000000000000000000000000000000000000000000000000000000000007C
+S123018000000000000000000000000000000000000000000000000000000000000000005C
+S12301A000000000000000000000000000000000000000000000000000000000000000003C
+S12301C000000000000000000000000000000000000000000000000000000000000000001C
+S12301E00000000000000000000000000000000000000000000000000000000000000000FC
+S9030000FC

as68hc11/code/test6.asm

@@ -0,0 +1,27 @@
+RAM    equ 0000h
+THIS   equ 0010h
+THAT   equ 0020h
+OTHER  equ 0030h
+LONG   equ 0080h
+  org RAM
+  bra THIS
+  org THIS
+  bra OTHER
+  org THAT
+princ:
+  inx
+  bra end
+  org OTHER
+  bra princ
+end:
+  bra LONG
+  org LONG
+  ldab LONG
+  rts
+
+
+
+
+
+
+

as68hc11/code/test6.s19

@@ -0,0 +1,17 @@
+S1230000200E0000000000000000000000000000201E000000000000000000000000000070
+S123002008200F0000000000000000000000000020EE204E00000000000000000000000009
+S123004000000000000000000000000000000000000000000000000000000000000000009C
+S123006000000000000000000000000000000000000000000000000000000000000000007C
+S1230080C680390000000000000000000000000000000000000000000000000000000000DD
+S12300A000000000000000000000000000000000000000000000000000000000000000003C
+S12300C000000000000000000000000000000000000000000000000000000000000000001C
+S12300E00000000000000000000000000000000000000000000000000000000000000000FC
+S12301000000000000000000000000000000000000000000000000000000000000000000DC
+S12301200000000000000000000000000000000000000000000000000000000000000000BC
+S123014000000000000000000000000000000000000000000000000000000000000000009C
+S123016000000000000000000000000000000000000000000000000000000000000000007C
+S123018000000000000000000000000000000000000000000000000000000000000000005C
+S12301A000000000000000000000000000000000000000000000000000000000000000003C
+S12301C000000000000000000000000000000000000000000000000000000000000000001C
+S12301E00000000000000000000000000000000000000000000000000000000000000000FC
+S9030000FC

as68hc11/code/test7.asm

@@ -0,0 +1,28 @@
+RAM    equ 0000h
+THIS   equ 0010h
+THAT   equ 0020h
+OTHER  equ 0030h
+LONG   equ 0080h
+  org RAM
+  inx
+  bra THIS
+  org THIS
+  bra OTHER
+  org THAT
+princ:
+  inx
+  bra end
+  org OTHER
+  bra princ
+end:
+  bra LONG
+  org LONG
+  ldab LONG
+  rts
+
+
+
+
+
+
+

as68hc11/code/test7.bin

@@ -0,0 +1 @@
+ 












 













 












 <20> N











































































ƀ9

as68hc11/code/test7.s19

@@ -0,0 +1,17 @@
+S123000008200E01010101010101010101010101201E01010101010101010101010101014D
+S123002008200F0101010101010101010101010120EE204E010101010101010101010101F0
+S123004001010101010101010101010101010101010101010101010101010101010101017C
+S123006001010101010101010101010101010101010101010101010101010101010101015C
+S1230080C680390101010101010101010101010101010101010101010101010101010101C0
+S12300A001010101010101010101010101010101010101010101010101010101010101011C
+S12300C00101010101010101010101010101010101010101010101010101010101010101FC
+S12300E00101010101010101010101010101010101010101010101010101010101010101DC
+S12301000101010101010101010101010101010101010101010101010101010101010101BC
+S123012001010101010101010101010101010101010101010101010101010101010101019C
+S123014001010101010101010101010101010101010101010101010101010101010101017C
+S123016001010101010101010101010101010101010101010101010101010101010101015C
+S123018001010101010101010101010101010101010101010101010101010101010101013C
+S12301A001010101010101010101010101010101010101010101010101010101010101011C
+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC

as68hc11/code/test8.asm

@@ -0,0 +1,16 @@
+RAM    equ 0000h
+THIS   equ 0010h
+END    equ 0020h
+  org RAM
+  inx
+  bra THIS
+  org THIS
+  ldab THIS
+  bra END
+  org END
+  ldab END
+  rts
+
+
+
+

as68hc11/code/test8.bin

@@ -0,0 +1 @@
+ 

as68hc11/code/test8.s19

@@ -0,0 +1,17 @@
+S123000008200D01010101010101010101010101C610200C0101010101010101010101018C
+S1230020C62039010101010101010101010101010101010101010101010101010101010180
+S123004001010101010101010101010101010101010101010101010101010101010101017C
+S123006001010101010101010101010101010101010101010101010101010101010101015C
+S123008001010101010101010101010101010101010101010101010101010101010101013C
+S12300A001010101010101010101010101010101010101010101010101010101010101011C
+S12300C00101010101010101010101010101010101010101010101010101010101010101FC
+S12300E00101010101010101010101010101010101010101010101010101010101010101DC
+S12301000101010101010101010101010101010101010101010101010101010101010101BC
+S123012001010101010101010101010101010101010101010101010101010101010101019C
+S123014001010101010101010101010101010101010101010101010101010101010101017C
+S123016001010101010101010101010101010101010101010101010101010101010101015C
+S123018001010101010101010101010101010101010101010101010101010101010101013C
+S12301A001010101010101010101010101010101010101010101010101010101010101011C
+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC

as68hc11/code/test9.asm

@@ -0,0 +1,39 @@
+INCLUDE equates.inc
+INCLUDE macros.inc
+  org RAM        
+  jmp BEGIN
+  szTitle rmb 'A','B',00h
+BEGIN:
+  ldx szTitle
+  bra DELAY10
+
+  ldab 01h        ; move 1 into register b
+  stab [PORTB]    ; light b0
+  ldaa [PORTB]    ; move contents of PORTB into register a
+  ldab [PORTB]    ; move contents of PORTB into register b
+
+  ldy 00h
+  ldy SCSR
+  staa iy,20h  
+
+waitchar1:
+  brclr ix,SCSR,20h,waitchar1 ; wait for RDRF
+; branch to waitchar1 if ix+SCSR bit 5 is clear
+
+  ldab RAM
+  cmpa RAM
+;  bne prend
+  inx
+  inx
+  inx
+  bra THIS
+  org THIS
+  ldab THIS
+  bra END
+  org END
+prend:
+  ldab END
+  rts
+
+
+

as68hc11/code/test9.s19

@@ -0,0 +1,17 @@
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+S12301C00101010101010101010101010101010101010101010101010101010101010101FC
+S12301E00101010101010101010101010101010101010101010101010101010101010101DC
+S9030000FC