; AUTHOR: SEAN KESSLER DATE:04/17/1999 ; PROGRAM: TALK.ASM ; PLATFORM:M68HC11 ; FUNCTION:TEST SWI INSTRUCTION EVENTCHAR equ 000h EVENTWORD equ 001h EVENTDWORD equ 002h EVENTVARCHAR equ 003h EVENTREGS equ 004h EVENTEND equ 0FFh SCDR equ 0102Fh ; data register SCSR equ 0102Eh ; status register EEPROM equ 0F800h ; start of EEPROM RAM equ 00000h ; base of code SWI equ 0FFF6h ; software interrupt vector lives here REGS equ 01000h ; start of REGS CONFIG equ 0103Fh ; CONFIG marks the end of REGS BPROT equ 01035h ; BPROT PPROG equ 0103Bh ; PPROG MEMLOC equ 80h ; 80h,81h are scratch pad STACK equ RAM+0FFh ; stack expands down from here org RAM ; base of code BEGIN equ * lds STACK ; initialize the stack START equ * ; start sync address bsr WRITEREGSEVENT ; bsr WRITEENDEVENT ; jmp START ; do it forever WRITESTRING equ * rts WRITEENDEVENT equ * ; write end event to the SCI ldab EVENTEND ; load the event type into register B bsr WRITECHAR ; write the event to the SCI rts ; return to caller WRITECHAREVENT equ * ; write a character event to the SCI pshb ; save contents of register B ldab EVENTCHAR ; load event type into register B bsr WRITECHAR ; write the event type to the SCI pulb ; restore contents of register B bsr WRITECHAR ; write the event data to the SCI rts ; return to caller WRITEREGSEVENT equ * ; write the registers out to the SCI ldab EVENTREGS ; load value of EVENTREGS into register B bsr WRITECHAR ; send the value out to the SCI ldd REGS ; get address of REGS into register D CONTINUEREGS equ * ; sync address psha ; save register A pshb ; save register B xgdx ; exchange D with X (X has current address) ldab ix,00h ; load byte at address in X to B register bsr WRITECHAR ; send the byte out to the SCI pulb ; restore register B pula ; restore register A addd 01h ; increment value in register D cpd CONFIG ; compare this value to address of CONFIG register ble CONTINUEREGS ; if it's less than or equal then keep going bsr WAITCHAR ; wait for a character rts ; return to caller WRITECHAR equ * ; write character from B register to SCDR ldaa [SCSR] ; get status into A register anda 80h ; check TDRE (transmit data register empty) beq WRITECHAR ; keep trying until SCI is ready for character stab [SCDR] ; write character from B register to SCDR rts ; return to caller WRITEWORD equ * ; write word in register D to the SCI psha ; save contents of register A bsr WRITECHAR ; write contents of B (hi byte) pulb ; restore contents of register A into B bsr WRITECHAR ; write contents of B (lo byte) rts ; return to caller READCHAR equ * ; read character from SCDR into B register psha ; save contents of register A RDCLOOP equ * ; wait loop ldaa [SCSR] ; get status into A register anda 20h ; is RDRF set (indicates we have char) beq RDCLOOP ; keep trying until RDRF is set ldab [SCDR] ; load character into B register pula ; save contents of register A rts ; return to caller WAITCHAR equ * ; wait for a character psha ; save contents of register A pshb ; save contents of register B bsr READCHAR ; read a character into B register pulb ; restore contents of register B pula ; restore contents of register A rts ; return to caller