427 lines
20 KiB
HTML
427 lines
20 KiB
HTML
|
|
<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
|
|
|
|
<!-- J & B IMAGING SERVICES, INC. email=jabis@aus.sig.net -->
|
|
<!-- J & B IMAGING SERVICES, INC. phone/fax=(512) 219 9517 -->
|
|
<!------ JRS HTML MAPPER/EDITOR (FrameMaker 5.5) V6.5 ------->
|
|
<!-- Jay Ridge Services, Inc phone/fax/ans mach=(512) 261-3148-->
|
|
<HTML>
|
|
|
|
<TITLE>
|
|
MC68HC11F1 Technical Data - HTML Created 04-11-1998</TITLE>
|
|
|
|
<BODY bgcolor=#FFFFFF>
|
|
|
|
<P>Click here for:
|
|
<BLOCKQUOTE><P><A HREF="/lit/manuals/mc68hc11f1td/outline1.html#oc3000010">Return to Outline</A>
|
|
<BR><A HREF="#txt000830">End of This file</A>
|
|
<BR><A HREF="c2.html#txt001330">Prior text</A>
|
|
</BLOCKQUOTE>
|
|
|
|
<H2 ALIGN=CENTER><A NAME="txt000010"></A>SECTION 3 <STRONG><BR>
|
|
</STRONG>CENTRAL PROCESSING UNIT</H2>
|
|
|
|
<P><A NAME="txt000020"></A>This section presents information on M68HC11
|
|
central processing unit (CPU) architecture. Data types, addressing
|
|
modes, the instruction set, and the extended addressing range required
|
|
to support this MCU's memory expansion feature are also included, as
|
|
are special operations such as subroutine calls and interrupts.
|
|
|
|
<P><A NAME="txt000030"></A>The CPU is designed to treat all peripheral,
|
|
I/O, and memory locations identically as addresses in the 64 Kbyte
|
|
memory map. This is referred to as memory-mapped I/O. There are no
|
|
special instructions for I/O that are separate from those used for
|
|
memory. This architecture also allows accessing an operand from an
|
|
external memory location with no execution-time penalty.
|
|
|
|
<H3><A NAME="txt000040"></A>3.1 CPU Registers</H3>
|
|
|
|
<P><A NAME="txt000050"></A>M68HC11 CPU registers are an integral part
|
|
of the CPU and are not addressed as if they were memory locations. The
|
|
seven registers, discussed in the following paragraphs, are shown in
|
|
Figure 3-1
|
|
.
|
|
|
|
<P ALIGN=CENTER><IMG ALT="c3f3-1" SRC="gifs/c3f3-1.gif" WIDTH="678"
|
|
HEIGHT="580" ALIGN="BOTTOM" BORDER="0">
|
|
|
|
<H4 ALIGN=CENTER><A NAME="txt000060"></A>Figure 3-1 Programming
|
|
Model</H4>
|
|
|
|
<H3><A NAME="txt000070"></A>3.1.1 Accumulators A, B, and D</H3>
|
|
|
|
<P><A NAME="txt000080"></A>Accumulators A and B are general-purpose
|
|
8-bit registers that hold operands and results of arithmetic
|
|
calculations or data manipulations. For some instructions, these two
|
|
accumulators are treated as a single double-byte (16-bit) accumulator
|
|
called accumulator D. Although most instructions can use accumulators A
|
|
or B interchangeably, the following exceptions apply:
|
|
|
|
<P><A NAME="txt000090"></A>The ABX and ABY instructions add the
|
|
contents of 8-bit accumulator B to the contents of 16-bit register X or
|
|
Y, but there are no equivalent instructions that use A instead of B.
|
|
|
|
<P><A NAME="txt000100"></A>The TAP and TPA instructions transfer data
|
|
from accumulator A to the condition code register, or from the
|
|
condition code register to accumulator A, however, there are no
|
|
equivalent instructions that use B rather than A.
|
|
|
|
<P><A NAME="txt000110"></A>The decimal adjust accumulator A (DAA)
|
|
instruction is used after binary-coded decimal (BCD) arithmetic
|
|
operations, but there is no equivalent BCD instruction to adjust
|
|
accumulator B.
|
|
|
|
<P><A NAME="txt000120"></A>The add, subtract, and compare instructions
|
|
associated with both A and B (ABA, SBA, and CBA) only operate in one
|
|
direction, making it important to plan ahead to ensure that the correct
|
|
operand is in the correct accumulator.
|
|
|
|
<H3><A NAME="txt000130"></A>3.1.2 Index Register X (IX)</H3>
|
|
|
|
<P><A NAME="txt000140"></A>The IX register provides a 16-bit indexing
|
|
value that can be added to the 8-bit offset provided in an instruction
|
|
to create an effective address. The IX register can also be used as a
|
|
counter or as a temporary storage register.
|
|
|
|
<H3><A NAME="txt000150"></A>3.1.3 Index Register Y (IY)</H3>
|
|
|
|
<P><A NAME="txt000160"></A>The 16-bit IY register performs an indexed
|
|
mode function similar to that of the IX register. However, most
|
|
instructions using the IY register require an extra byte of machine
|
|
code and an extra cycle of execution time because of the way the opcode
|
|
map is implemented. Refer to
|
|
<A HREF="#txt000630">
|
|
3.3 Opcodes and Operands</A>
|
|
<STRONG> </STRONG>for further information.
|
|
|
|
<H3><A NAME="txt000170"></A>3.1.4 Stack Pointer (SP)</H3>
|
|
|
|
<P><A NAME="txt000180"></A>The M68HC11 CPU has an automatic program
|
|
stack. This stack can be located anywhere in the address space and can
|
|
be any size up to the amount of memory available in the system.
|
|
Normally the SP is initialized by one of the first instructions in an
|
|
application program. The stack is configured as a data structure that
|
|
grows downward from high memory to low memory. Each time a new byte is
|
|
pushed onto the stack, the SP is decremented. Each time a byte is
|
|
pulled from the stack, the SP is incremented. At any given time, the SP
|
|
holds the 16-bit address of the next free location in the stack.
|
|
Figure 3-2
|
|
is a summary of SP operations.
|
|
|
|
<P ALIGN=CENTER><IMG ALT="c3f3-2" SRC="gifs/c3f3-2.gif" WIDTH="681"
|
|
HEIGHT="693" ALIGN="BOTTOM" BORDER="0">
|
|
|
|
<H4 ALIGN=CENTER><A NAME="txt000190"></A>Figure 3-2 Stacking
|
|
Operations</H4>
|
|
|
|
<P><A NAME="txt000200"></A>When a subroutine is called by a jump to
|
|
subroutine (JSR) or branch to subroutine (BSR) instruction, the address
|
|
of the instruction after the JSR or BSR is automatically pushed onto
|
|
the stack, least significant byte first. When the subroutine is
|
|
finished, a return from subroutine (RTS) instruction is executed. The
|
|
RTS pulls the previously stacked return address from the stack, and
|
|
loads it into the program counter. Execution then continues at this
|
|
recovered return address.
|
|
|
|
<P><A NAME="txt000210"></A>When an interrupt is recognized, the current
|
|
instruction finishes normally, the return address (the current value in
|
|
the program counter) is pushed onto the stack, all of the CPU registers
|
|
are pushed onto the stack, and execution continues at the address
|
|
specified by the vector for the interrupt. At the end of the interrupt
|
|
service routine, an RTI instruction is executed. The RTI instruction
|
|
causes the saved registers to be pulled off the stack in reverse order.
|
|
Program execution resumes at the return address.
|
|
|
|
<P><A NAME="txt000220"></A>There are instructions that push and pull
|
|
the A and B accumulators and the X and Y index registers. These
|
|
instructions are often used to preserve program context. For example,
|
|
pushing accumulator A onto the stack when entering a subroutine that
|
|
uses accumulator A, and then pulling accumulator A off the stack just
|
|
before leaving the subroutine, ensures that the contents of a register
|
|
will be the same after returning from the subroutine as it was before
|
|
starting the subroutine.
|
|
|
|
<H3><A NAME="txt000230"></A>3.1.5 Program Counter (PC)</H3>
|
|
|
|
<P><A NAME="txt000240"></A>The program counter, a 16-bit register,
|
|
contains the address of the next instruction to be executed. After
|
|
reset, the program counter is initialized from one of six possible
|
|
vectors, depending on operating mode and the cause of reset.
|
|
|
|
<H4 ALIGN=CENTER><A NAME="txt000250"></A>Table 3-1 Reset Vector Comparison</H4>
|
|
|
|
<P>
|
|
|
|
<CENTER><TABLE BORDER>
|
|
<TR>
|
|
<TD ALIGN=CENTER><A NAME="txt000260"></A> </TD>
|
|
<TH ALIGN=CENTER><A NAME="txt000270"></A>POR or <IMG ALT="Overbar
|
|
RESET" SRC="/lit/overbar/reset.gif" ALIGN="MIDDLE" BORDER="0"> Pin</TH>
|
|
<TH ALIGN=CENTER><A NAME="txt000280"></A>Clock Monitor</TH>
|
|
<TH ALIGN=CENTER><A NAME="txt000290"></A>COP Watchdog</TH>
|
|
</TR><TR>
|
|
<TD ALIGN=CENTER><A NAME="txt000300"></A>Normal</TD>
|
|
<TD ALIGN=CENTER><A NAME="txt000310"></A>$FFFE, F</TD>
|
|
<TD ALIGN=CENTER><A NAME="txt000320"></A>$FFFC, D</TD>
|
|
<TD ALIGN=CENTER><A NAME="txt000330"></A>$FFFA, B</TD>
|
|
</TR><TR>
|
|
<TD ALIGN=CENTER><A NAME="txt000340"></A>Test or Boot</TD>
|
|
<TD ALIGN=CENTER><A NAME="txt000350"></A>$BFFE, F</TD>
|
|
<TD ALIGN=CENTER><A NAME="txt000360"></A>$BFFC, D</TD>
|
|
<TD ALIGN=CENTER><A NAME="txt000370"></A>$BFFA, B</TD>
|
|
</TR>
|
|
</TABLE></CENTER>
|
|
|
|
<H3><A NAME="txt000380"></A>3.1.6 Condition Code Register (CCR) </H3>
|
|
|
|
<P><A NAME="txt000390"></A>This 8-bit register contains five condition
|
|
code indicators (C, V, Z, N, and H), two interrupt masking bits, (I and
|
|
X) and a stop disable bit (S). In the M68HC11 CPU, condition codes are
|
|
automatically updated by most instructions. For example, load
|
|
accumulator A (LDAA) and store accumulator A (STAA) instructions
|
|
automatically set or clear the N, Z, and V condition code flags.
|
|
Pushes, pulls, add B to X (ABX), add B to Y (ABY), and
|
|
transfer/exchange instructions do not affect the condition codes. Refer
|
|
to
|
|
Table 3-2
|
|
, which shows what condition codes are affected by a particular
|
|
instruction.
|
|
|
|
<H3><A NAME="txt000400"></A>3.1.6.1 Carry/Borrow (C) </H3>
|
|
|
|
<P><A NAME="txt000410"></A>The C bit is set if the arithmetic logic
|
|
unit (ALU) performs a carry or borrow during an arithmetic operation.
|
|
The C bit also acts as an error flag for multiply and divide
|
|
operations. Shift and rotate instructions operate with and through the
|
|
carry bit to facilitate multiple-word shift operations.
|
|
|
|
<H3><A NAME="txt000420"></A>3.1.6.2 Overflow (V)</H3>
|
|
|
|
<P><A NAME="txt000430"></A>The overflow bit is set if an operation
|
|
causes an arithmetic overflow. Otherwise, the V bit is cleared.
|
|
|
|
<H3><A NAME="txt000440"></A>3.1.6.3 Zero (Z)</H3>
|
|
|
|
<P><A NAME="txt000450"></A>The Z bit is set if the result of an
|
|
arithmetic, logic, or data manipulation operation is zero. Otherwise,
|
|
the Z bit is cleared. Compare instructions do an internal implied
|
|
subtraction and the condition codes, including Z, reflect the results
|
|
of that subtraction. A few operations (INX, DEX, INY, and DEY) affect
|
|
the Z bit and no other condition flags. For these operations, only =
|
|
and - conditions can be determined.
|
|
|
|
<H3><A NAME="txt000460"></A>3.1.6.4 Negative (N)</H3>
|
|
|
|
<P><A NAME="txt000470"></A>The N bit is set if the result of an
|
|
arithmetic, logic, or data manipulation operation is negative (MSB =
|
|
1). Otherwise, the N bit is cleared. A result is said to be negative if
|
|
its most significant bit (MSB) is a one. A quick way to test whether
|
|
the contents of a memory location has the MSB set is to load it into an
|
|
accumulator and then check the status of the N bit.
|
|
|
|
<H3><A NAME="txt000480"></A>3.1.6.5 Interrupt Mask (I)</H3>
|
|
|
|
<P><A NAME="txt000490"></A>The interrupt request (IRQ) mask (I bit) is
|
|
a global mask that disables all maskable interrupt sources. While the I
|
|
bit is set, interrupts can become pending, but the operation of the CPU
|
|
continues uninterrupted until the I bit is cleared. After any reset,
|
|
the I bit is set by default and can only be cleared by a software
|
|
instruction. When an interrupt is recognized, the I bit is set after
|
|
the registers are stacked, but before the interrupt vector is fetched.
|
|
After the interrupt has been serviced, a return from interrupt
|
|
instruction is normally executed, restoring the registers to the values
|
|
that were present before the interrupt occurred. Normally, the I bit is
|
|
zero after a return from interrupt is executed. Although the I bit can
|
|
be cleared within an interrupt service routine, “nesting”
|
|
interrupts in this way should only be done when there is a clear
|
|
understanding of latency and of the arbitration mechanism. Refer to
|
|
<A HREF="c5a.html#txt000010">
|
|
SECTION 5 RESETS AND INTERRUPTS</A>
|
|
.
|
|
|
|
<H3><A NAME="txt000500"></A>3.1.6.6 Half Carry (H)</H3>
|
|
|
|
<P><A NAME="txt000510"></A>The H bit is set when a carry occurs between
|
|
bits 3 and 4 of the arithmetic logic unit during an ADD, ABA, or ADC
|
|
instruction. Otherwise, the H bit is cleared. Half carry is used during
|
|
BCD operations.
|
|
|
|
<H3><A NAME="txt000520"></A>3.1.6.7 X Interrupt Mask (X)</H3>
|
|
|
|
<P><A NAME="txt000530"></A>The <IMG ALT="Overbar XIRQ"
|
|
SRC="/lit/overbar/xirq.gif" ALIGN="MIDDLE" BORDER="0"> mask (X) bit
|
|
disables interrupts from the <IMG ALT="Overbar XIRQ"
|
|
SRC="/lit/overbar/xirq.gif" ALIGN="MIDDLE" BORDER="0"> pin. After any
|
|
reset, X is set by default and must be cleared by a software
|
|
instruction. When an <IMG ALT="Overbar XIRQ"
|
|
SRC="/lit/overbar/xirq.gif" ALIGN="MIDDLE" BORDER="0"> interrupt is
|
|
recognized, the X and I bits are set after the registers are stacked,
|
|
but before the interrupt vector is fetched. After the interrupt has
|
|
been serviced, an RTI instruction is normally executed, causing the
|
|
registers to be restored to the values that were present before the
|
|
interrupt occurred. The X interrupt mask bit is set only by hardware
|
|
(<IMG ALT="Overbar RESET" SRC="/lit/overbar/reset.gif" ALIGN="MIDDLE"
|
|
BORDER="0"> or <IMG ALT="Overbar XIRQ" SRC="/lit/overbar/xirq.gif"
|
|
ALIGN="MIDDLE" BORDER="0"> acknowledge). X is cleared only by program
|
|
instruction (TAP, where the associated bit of A is zero; or RTI, where
|
|
bit 6 of the value loaded into the CCR from the stack has been
|
|
cleared). There is no hardware action for clearing X.
|
|
|
|
<H3><A NAME="txt000540"></A>3.1.6.8 Stop Disable (S)</H3>
|
|
|
|
<P><A NAME="txt000550"></A>Setting the STOP disable (S) bit prevents
|
|
the STOP instruction from putting the M68HC11 into a low-power stop
|
|
condition. If the CPU encounters a STOP instruction while the S bit is
|
|
set, it is treated as a no-operation (NOP) instruction, and processing
|
|
continues to the next instruction. S is set by reset — STOP
|
|
disabled by default.
|
|
|
|
<H3><A NAME="txt000560"></A>3.2 Data Types</H3>
|
|
|
|
<P><A NAME="txt000570"></A>The M68HC11 CPU supports the following data
|
|
types:
|
|
|
|
<UL>
|
|
|
|
<LI><A NAME="txt000580"></A>Bit data
|
|
|
|
<LI><A NAME="txt000590"></A>8-bit and 16-bit signed and unsigned
|
|
integers
|
|
|
|
<LI><A NAME="txt000600"></A>16-bit unsigned fractions
|
|
|
|
<LI><A NAME="txt000610"></A>16-bit addresses
|
|
</UL>
|
|
<P><A NAME="txt000620"></A>A byte is eight bits wide and can be
|
|
accessed at any byte location. A word is composed of two consecutive
|
|
bytes with the most significant byte at the lower value address.
|
|
Because the M68HC11 is an 8-bit CPU, there are no special requirements
|
|
for alignment of instructions or operands.
|
|
|
|
<H3><A NAME="txt000630"></A>3.3 Opcodes and Operands</H3>
|
|
|
|
<P><A NAME="txt000640"></A>The M68HC11 family of microcontrollers uses
|
|
8-bit opcodes. Each opcode identifies a particular instruction and
|
|
associated addressing mode to the CPU. Several opcodes are required to
|
|
provide each instruction with a range of addressing capabilities. Only
|
|
256 opcodes would be available if the range of values were restricted
|
|
to the number able to be expressed in 8-bit binary numbers.
|
|
|
|
<P><A NAME="txt000650"></A>A four-page opcode map has been implemented
|
|
to expand the number of instructions. An additional byte, called a
|
|
prebyte, directs the processor from page 0 of the opcode map to one of
|
|
the other three pages. As its name implies, the additional byte
|
|
precedes the opcode.
|
|
|
|
<P><A NAME="txt000660"></A>A complete instruction consists of a
|
|
prebyte, if any, an opcode, and zero, one, two, or three operands. The
|
|
operands contain information the CPU needs for executing the
|
|
instruction. Complete instructions can be from one to five bytes long.
|
|
|
|
<H3><A NAME="txt000670"></A>3.4 Addressing Modes</H3>
|
|
|
|
<P><A NAME="txt000680"></A>Six addressing modes can be used to access
|
|
memory: immediate, direct, extended, indexed, inherent, and relative.
|
|
These modes are detailed in the following paragraphs. All modes except
|
|
inherent mode use an effective address. The effective address is the
|
|
memory address from which the argument is fetched or stored, or the
|
|
address from which execution is to proceed. The effective address can
|
|
be specified within an instruction, or it can be calculated.
|
|
|
|
<H3><A NAME="txt000690"></A>3.4.1 Immediate </H3>
|
|
|
|
<P><A NAME="txt000700"></A>In the immediate addressing mode an argument
|
|
is contained in the byte(s) immediately following the opcode. The
|
|
number of bytes following the opcode matches the size of the register
|
|
or memory location being operated on. There are two-, three-, and four-
|
|
(if prebyte is required) byte immediate instructions. The effective
|
|
address is the address of the byte following the instruction.
|
|
|
|
<H3><A NAME="txt000710"></A>3.4.2 Direct </H3>
|
|
|
|
<P><A NAME="txt000720"></A>In the direct addressing mode, the low-order
|
|
byte of the operand address is contained in a single byte following the
|
|
opcode, and the high-order byte of the address is assumed to be $00.
|
|
Addresses $00–$FF are thus accessed directly, using two-byte
|
|
instructions. Execution time is reduced by eliminating the additional
|
|
memory access required for the high-order address byte. In most
|
|
applications, this 256-byte area is reserved for frequently referenced
|
|
data. In M68HC11 MCUs, the memory map can be configured for
|
|
combinations of internal registers, RAM, or external memory to occupy
|
|
these addresses.
|
|
|
|
<H3><A NAME="txt000730"></A>3.4.3 Extended </H3>
|
|
|
|
<P><A NAME="txt000740"></A>In the extended addressing mode, the
|
|
effective address of the argument is contained in two bytes following
|
|
the opcode byte. These are three-byte instructions (or four-byte
|
|
instructions if a prebyte is required). One or two bytes are needed for
|
|
the opcode and two for the effective address.
|
|
|
|
<H3><A NAME="txt000750"></A>3.4.4 Indexed</H3>
|
|
|
|
<P><A NAME="txt000760"></A>In the indexed addressing mode, an 8-bit
|
|
unsigned offset contained in the instruction is added to the value
|
|
contained in an index register (IX or IY). The sum is the effective
|
|
address. This addressing mode allows referencing any memory location in
|
|
the 64 Kbyte address space. These are two- to five-byte instructions,
|
|
depending on whether or not a prebyte is required.
|
|
|
|
<H3><A NAME="txt000770"></A>3.4.5 Inherent</H3>
|
|
|
|
<P><A NAME="txt000780"></A>In the inherent addressing mode, all the
|
|
information necessary to execute the instruction is contained in the
|
|
opcode. Operations that use only the index registers or accumulators,
|
|
as well as control instructions with no arguments, are included in this
|
|
addressing mode. These are one- or two-byte instructions.
|
|
|
|
<H3><A NAME="txt000790"></A>3.4.6 Relative</H3>
|
|
|
|
<P><A NAME="txt000800"></A>The relative addressing mode is used only
|
|
for branch instructions. If the branch condition is true, an 8-bit
|
|
signed offset included in the instruction is added to the contents of
|
|
the program counter to form the effective branch address. Otherwise,
|
|
control proceeds to the next instruction. These are usually two-byte
|
|
instructions.
|
|
|
|
<H3><A NAME="txt000810"></A>3.5 Instruction Set</H3>
|
|
|
|
<P><A NAME="txt000820"></A>Refer to
|
|
Table 3-2
|
|
, which shows all the M68HC11 instructions in all possible addressing
|
|
modes. For each instruction, the table shows the operand construction,
|
|
the number of machine code bytes, and execution time in CPU E clock
|
|
cycles.
|
|
|
|
<H4 ALIGN=CENTER><A NAME="txt000830"></A>Table 3-2 Instruction Set </H4>
|
|
|
|
<P ALIGN=CENTER><IMG ALT="c3t3-2a" SRC="gifs/c3t3-2a.gif" WIDTH="645"
|
|
HEIGHT="838" ALIGN="BOTTOM" BORDER="0">
|
|
|
|
<P ALIGN=CENTER><IMG ALT="c3t3-2b" SRC="gifs/c3t3-2b.gif" WIDTH="646"
|
|
HEIGHT="802" ALIGN="BOTTOM" BORDER="0">
|
|
|
|
<P ALIGN=CENTER><IMG ALT="c3t3-2c" SRC="gifs/c3t3-2c.gif" WIDTH="646"
|
|
HEIGHT="842" ALIGN="BOTTOM" BORDER="0">
|
|
|
|
<P ALIGN=CENTER><IMG ALT="c3t3-2d" SRC="gifs/c3t3-2d.gif" WIDTH="645"
|
|
HEIGHT="853" ALIGN="BOTTOM" BORDER="0">
|
|
|
|
<P ALIGN=CENTER><IMG ALT="c3t3-2e" SRC="gifs/c3t3-2e.gif" WIDTH="645"
|
|
HEIGHT="833" ALIGN="BOTTOM" BORDER="0">
|
|
|
|
<P ALIGN=CENTER><IMG ALT="c3t3-2f" SRC="gifs/c3t3-2f.gif" WIDTH="644"
|
|
HEIGHT="817" ALIGN="BOTTOM" BORDER="0">
|
|
|
|
<P ALIGN=CENTER><IMG ALT="c3t3-2g" SRC="gifs/c3t3-2g.gif" WIDTH="644"
|
|
HEIGHT="596" ALIGN="BOTTOM" BORDER="0">
|
|
|
|
<P>Click here for:
|
|
<BLOCKQUOTE><P><A HREF="/lit/manuals/mc68hc11f1td/outline1.html#oc3000010">Return to Outline</A>
|
|
<BR><A HREF="#txt000010">Beginning of This file</A>
|
|
<BR><A HREF="c4a.html#txt000010">Next text</A>
|
|
</BLOCKQUOTE>
|
|
|
|
</BODY>
|
|
</HTML>
|