70 lines
3.1 KiB
NASM
70 lines
3.1 KiB
NASM
; AUTHOR: SEAN KESSLER DATE:04/17/1999
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; PROGRAM: TALK.ASM
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; PLATFORM:M68HC11
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; FUNCTION:TEST SCI BASED COMMUNICATIONS ON CONTROLLER
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BAUD equ 0102Bh ; baud register
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SCCR2 equ 0102Dh ; main control register for SCI subsystem
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SCSR equ 0102Eh ; status register
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SCDR equ 0102Fh ; data register
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SPCR equ 01028h
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PORTD equ 01008h ; io configuration
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RAM equ 00000h ; base of code
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EEPROM equ 0F800h ; base of EEPROM
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STACK equ RAM+0FFh ; stack expands down from here
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LENGTH equ 0Bh
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org RAM ; base of code
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lds STACK ; initialize the stack
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START equ *
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; bsr INITSCI ; initialize communications on controller
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; bsr GETACK ; send break to host and wait for acknowledgement
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ldab 'S' ; load 'S' into register B
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bsr WRITECHAR ; send the character
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ldab 'E' ; load 'E' into register B
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bsr WRITECHAR ; send the character
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ldab 'A' ; load 'A' into register B
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bsr WRITECHAR ; send the character
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ldab 'N' ; load 'N' into register B
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bsr WRITECHAR ; send the character
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jmp START ; do it forever
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READCHAR equ * ; read character from SCDR into B register
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ldab 00h ; clear out B register
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ldaa [SCSR] ; get status into A register
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anda 20h ; is RDRF set (indicates we have char)
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beq READCHAR ; keep trying until RDRF is set
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ldab [SCDR] ; load character into B register
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rts ; return to caller
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WRITECHAR equ * ; write character to SCDR from B register
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ldaa [SCSR] ; get status into A register
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anda 80h ; check TDRE (transmit data register empty)
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beq WRITECHAR ; keep trying until SCI is ready for character
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stab [SCDR] ; write character from B register to SCDR
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rts ; return to caller
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INITSCI equ * ; controller initialization
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ldx SPCR ; load SPSC address into x register
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bset ix,0h,20h ; put port D in wire or mode
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ldaa 0A2h ; initialize SCI & restart BAUD rate divider
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staa [BAUD] ; do it
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ldaa 0Ch ; enable transmit/receive
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staa [SCCR2] ; do it
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rts ; return to caller
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GETACK equ * ; wait for signal from user
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ldx SCCR2 ; load SCCR2 address into index register x
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bset ix,00h,01h ; set bit zero in SCCR2, send break
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ldx PORTD ; load PORTD address into index register x
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clrbrk equ * ; sync address
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brset ix,00h,01h,clrbrk ; wait for start bit
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ldx SCCR2 ; load SCCR2 address into x register
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bclr ix,00h,01h ; clear the break
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waitchar equ * ; sync address
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ldx SCSR ; load address of SCDR into x register
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brclr ix,00h,20h,waitchar ; wait for a character
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ldaa [SCDR] ; load character into register A
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rts ; return to caller
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