94 lines
4.3 KiB
NASM
94 lines
4.3 KiB
NASM
; AUTHOR: SEAN KESSLER DATE:04/17/1999
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; PROGRAM: TALK.ASM
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; PLATFORM:M68HC11
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; FUNCTION:TEST SWI INSTRUCTION
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EVENTCHAR equ 000h
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EVENTWORD equ 001h
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EVENTDWORD equ 002h
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EVENTVARCHAR equ 003h
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EVENTREGS equ 004h
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EVENTEND equ 0FFh
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SCDR equ 0102Fh ; data register
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SCSR equ 0102Eh ; status register
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EEPROM equ 0F800h ; start of EEPROM
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RAM equ 00000h ; base of code
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SWI equ 0FFF6h ; software interrupt vector lives here
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REGS equ 01000h ; start of REGS
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CONFIG equ 0103Fh ; CONFIG marks the end of REGS
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BPROT equ 01035h ; BPROT
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PPROG equ 0103Bh ; PPROG
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MEMLOC equ 80h ; 80h,81h are scratch pad
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STACK equ RAM+0FFh ; stack expands down from here
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org RAM ; base of code
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BEGIN equ *
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lds STACK ; initialize the stack
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START equ * ; start sync address
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bsr WRITEREGSEVENT ;
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bsr WRITEENDEVENT ;
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jmp START ; do it forever
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WRITESTRING equ *
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rts
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WRITEENDEVENT equ * ; write end event to the SCI
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ldab EVENTEND ; load the event type into register B
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bsr WRITECHAR ; write the event to the SCI
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rts ; return to caller
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WRITECHAREVENT equ * ; write a character event to the SCI
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pshb ; save contents of register B
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ldab EVENTCHAR ; load event type into register B
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bsr WRITECHAR ; write the event type to the SCI
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pulb ; restore contents of register B
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bsr WRITECHAR ; write the event data to the SCI
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rts ; return to caller
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WRITEREGSEVENT equ * ; write the registers out to the SCI
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ldab EVENTREGS ; load value of EVENTREGS into register B
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bsr WRITECHAR ; send the value out to the SCI
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ldd REGS ; get address of REGS into register D
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CONTINUEREGS equ * ; sync address
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psha ; save register A
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pshb ; save register B
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xgdx ; exchange D with X (X has current address)
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ldab ix,00h ; load byte at address in X to B register
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bsr WRITECHAR ; send the byte out to the SCI
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pulb ; restore register B
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pula ; restore register A
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addd 01h ; increment value in register D
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cpd CONFIG ; compare this value to address of CONFIG register
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ble CONTINUEREGS ; if it's less than or equal then keep going
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bsr WAITCHAR ; wait for a character
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rts ; return to caller
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WRITECHAR equ * ; write character from B register to SCDR
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ldaa [SCSR] ; get status into A register
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anda 80h ; check TDRE (transmit data register empty)
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beq WRITECHAR ; keep trying until SCI is ready for character
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stab [SCDR] ; write character from B register to SCDR
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rts ; return to caller
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WRITEWORD equ * ; write word in register D to the SCI
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psha ; save contents of register A
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bsr WRITECHAR ; write contents of B (hi byte)
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pulb ; restore contents of register A into B
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bsr WRITECHAR ; write contents of B (lo byte)
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rts ; return to caller
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READCHAR equ * ; read character from SCDR into B register
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psha ; save contents of register A
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RDCLOOP equ * ; wait loop
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ldaa [SCSR] ; get status into A register
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anda 20h ; is RDRF set (indicates we have char)
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beq RDCLOOP ; keep trying until RDRF is set
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ldab [SCDR] ; load character into B register
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pula ; save contents of register A
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rts ; return to caller
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WAITCHAR equ * ; wait for a character
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psha ; save contents of register A
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pshb ; save contents of register B
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bsr READCHAR ; read a character into B register
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pulb ; restore contents of register B
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pula ; restore contents of register A
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rts ; return to caller
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